PROFILE
A motivated and enthusiastic Process Development Engineer with four years of professional experience in semiconductor industry (Ph.D. in Electrical Engineering). Strong understanding of semiconductor devices, thin films, material science and IC Processing, some experience of IC design and layout
TECHNICAL SUMMARY
• Over four years of experience in semiconductor industry as process development engineer
• Strong experience of LPCVD poly and TEOS processes
• Strong experience of various thin film deposition techniques such as LPCVD, PECVD and PVD
• Knowledge of various thin film characterization techniques
• Research experience on fabrication of thin film transistors
• Research experience on low temperature fabrication of solar cells
• Co-authored a research paper on solar cells fabrication
• Knowledge and understanding of semiconductor devices and device physics
• Understanding of fundamentals of Integrated Circuit Design
• Worked with Mentor Graphics’ IC layout and design tools
• Knowledge of hardware description language (VHDL)
EMPLOYMENT HISTORY
11/20004 – Present Process Development Engineer, Infineon Technologies/ Qimonda, Dresden, Germany
Working as Development Engineer for LPCVD Poly/TEOS processes within thin films department.
• Involved in the process development of future generation DRAM and FLASH technologies
- Developed a process for deposition of silicon-germanium thin films for gate stack of MOS transistor
- Invented a process for deposition of ‘Hemispherical Silicon-Germanium Grains’ for capacitor formation in a deep trench on LPCVD batch furnace leading to filing of a U.S patent
- Developed various phosphorous doped and un-doped amorphous/polysilicon processes for DRAM and FLASH technologies
• Developed TEOS based LPCVD oxide processes
• Knowledge of process control and optimisation methodologies such as SPC
• Various trainings on job include Design of Experiment (DOE), Effective Presentation, Challenging Improvement in Productivity and Speed (CHIPS), Cycle time improvement, Statistical Process Control (SPC), Failure Mode Effect Analysis (FMEA) etc
08/2000 – 11/2004 Research Assistant, Department of Electrical Engineering
University of Arkansas, Fayetteville, AR 72701, U.S.A
Carried out research on “Low Temperature Fabrication of Polysilicon Thin Film Transistors (TFT’s)”
• Developed a process for fabricating TFT’s at low temperature for flexible displays
• Deposited and characterized silicon nitride films for gate dielectric applications using plasma enhanced chemical vapour deposition
• Produced excellent results on “Metal Induced Lateral Crystallization of Hydrogenated Amorphous Silicon” leading to master’s degree in electrical engineering
• Developed strong understanding of various thin film deposition techniques such as PECVD, sputtering, thermal evaporation etc
• Hands-on experience of various processing steps such as oxidation, photolithography, diffusion, wet etching, reactive ion etching, wire bonding, and wafer dicing
Primary responsibilities included maintenance of Photovoltaic Lab equipped with various thin film deposition systems such as PECVD, sputtering and thermal evaporation, and the maintenance of IC fabrication laboratory
01/2003 – 05/2003 Teaching Assistant, Department of Electrical Engineering
University of Arkansas, Fayetteville, AR 72701, U.S.A
Taught a graduate level IC fabrication lab
• Helped students understand the fabrication process and assisted them to fabricate bipolar devices, MOS devices and solar cells
• Trained students on operating oxidation furnace, mask aligner, spin-coating system, I-V and C-V measuring system, curve tracer and thermal evaporator
EDUCATION
2002 – 2005: Ph.D. in Electrical Engineering, University of Arkansas, Fayetteville, U.S.A
(GPA 3.6/4.0)
Dissertation: A Low Temperature Process for Fabrication of Thin Film Transistors.
Courses included: Semiconductor Devices, IC Fabrication Technology, IC Fabrication Lab, Electronic Packaging, Design and Fabrication of Solar Cells, Solid State Physics, Special Semiconductor Devices, Intro to VLSI Design, IC Design lab I, IC Design lab II, ASIC Design, Advanced Microwave Design, FPGA lab, Computer Architecture and Design, Low Power Digital Systems.
2000 – 2002 Masters in Electrical Engineering, University of Arkansas, Fayetteville, U.S.A
(GPA 3.78/4.0)
Thesis: Analysis of Aluminium Enhanced Lateral Crystallization of Hydrogenated Amorphous Silicon.
1995 – 1999 Bachelor of Science in Electrical Engineering, Aligarh Muslim University, India
Project: PC Based Speed Control of Separately Excited DC Motor.
COMPUTER SKILLS
• VHDL
• C / C++ programming
• UNIX Shell Programming
• Assembly language programming of MIPS, Motorola 68000 and Intel 8085 & 8086
• Mentor Graphics
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