“An IC layout designer with extensive experience in Silicon Valley and Asia”
QUALIFICATION
Experience with layout tools; Cadence 6.1 VXL, and Mentor
Experience with verification tools; Calibre DRC/LVS/ERC/ANT
Experience with planning, scheduling and all levels through chip tapeout
Experience with digital memories, SRAM, I/O and integration of I/O’s ring
Experience with analog circuits
PROCESSES
28nm Global Foundries, 32nm, 45nm, 6nm, 90nm, 110nm Spansion process
EXPERIENCE
07/09 – 04/11 Global Foundries Layout manager for analog 28nm IP testchip and product. PLL, TMON, CMON, IO, PCIe, DAC, Bandgap and standard cells.
03/09 – 06/09 Global Foundries Contract layout for 28nm process testchip tiles.
03/98 – 02/09 Spansion Senior mask layout engineer. Working as a project lead for high density flash memories. I was in Penang, Malaysia for 14 months to help staff, train and produce the first tapeout for the new design center.
09/95 – 11/95 Zycor Corporation Update layout to incorporate schematic edits into existing layout. (Contract)
04/95 – 09/95 Paradigm SRAM chip. (Contract)
01/95 – 04/95 National Semi Planning and layout of AMS circuits. (Contract)
04/94 – 12/94 Wafer Scale Inc. ESD structures and pad ring development. On-site training of Israel’s layout team in PLD layout and process. (Contract)
02/94 – 04/94 AMD Planning and layout of 4Mb flash product. (Contract)
11/93 – 02/94 National Semi Planning and layout of AMS circuits. (Contract)
04/93 – 11/93 SiArc Gate ...
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