Education:
Masters in Computer Engineering - George Mason University, VA. GPA – 3.54 Jan. 2012.
Course Work: Digital System Design with VHDL, Microprocessors, MOS Electronic Devices, VLSI Test Concepts, Cryptography and Network Security, Digital Integrated Circuits, Computer Network Architectures and Protocols, VLSI design for ASICs.
Thesis: Compact Implementations and Benchmarking of Two SHA-3 Finalists BLAKE and JH on FPGAs.
Bachelors in Electronics and Communication Engineering - Vignan Engineering College, India. GPA – 3.31 May. 2009.
Technical Skills:
• Programming Languages : C, Assembly level programming, VHDL, Verilog, SystemVerilog, Perl.
• Operating Systems : Windows XP/Vista/7, Mac OS, Linux.
• Tools : Xilinx ISE, Altera Quartus II, Synplify Pro, ModelSim, MultiSim, Matlab,
Cadence, Pspice, Microwind, Wireshark, TetraMax, Design Compiler, PrimeTime, Formality, IC Compiler.
• Other Software’s : Microsoft Office, Open Office, Microsoft Visio, LaTeX.
• Miscellaneous : Excellent troubleshooting and debugging skills and also knowledge on
Communication Protocols (TCP/IP, FTP)
Work Experience:
• Graduate Research Student, Cryptographic Engineering Research Group (GMU, VA) (Jan. 2010 – Present)
- Designed and implemented compact architectures of Two SHA-3 Finalists BLAKE and JH for Spartan-3 FPGAs. The different implementations include both distributed RAM version which uses pure logic and block RAM version which uses embedded elements for storage.
- Benchmarking of all the implementations using hardware tool ATHENa for achieving maximum throughput/area ratio.
- Other research interests include excessive study of architectural features of FPGA, Low-Area designing and True Random Number Generators.
• Graduate Teaching Assistant, Electrical and Computer Engineering Dept. (GMU, VA) (Aug. 2010 – May. 2011)
• Courses: Basic Electronics Lab, Digital System Design, Microprocessors
- Assist students in getting familiar with lab equipment, information about basic circuits and MSP430 debugging using IAR workbench.
- Tutor students on weekly basis to help in ongoing course/lab work and assignments.
Projects Undertaken:
• ASIC Design - ASIC Implementation of Compact BLAKE-32
- Compact architecture of BLAKE-32 is optimized and implemented on ASICs using 90nm technology.
- Implementation includes synthesis of the design, area optimization, timing analysis and Floor-planning using Synopsys ASIC tools like Design Vision, PrimeTime, IC Compiler.
- Test patters are generated and functionality is verified using TetraMax and VCS.
• Digital Design with VHDL - Implementations of BLAKE
- Designed and simulated both 32-bit & 64-bit variants of BLAKE for FPGAs.
- Designed different architectures of both BLAKE-32 & BLAKE-64, which includes folded and unrolled architectures, optimized for better throughput/area ratio.
- Simulations and assertion based verifications are performed at different levels to achieve post place route functionality using Xilinx Design Suite and Modelsim SE.
• Cryptography and Network Security - Low Area Implementations of BLAKE-32
- Designed and implemented area constraint designs of BLAKE-32 on Spartan3 FPGA using VHDL language.
- Developed low area architectures of BLAKE-32, which uses minimal logic resources and an embedded storage element. All the designs were simulated and optimized for better throu...
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