PROFESSIONAL SUMMARY
Bachelors Degree in Material Science Engineering with over 10 years of semiconductor industry experience
Accomplished photolithography engineer with proven success in high volume semiconductor manufacturing
Extensive experience analyzing technical data and driving actions based on the results
Collaborative, engaging work partner who excels in cross-functional teamwork in the areas of product transfers, new part introduction, process development and yield improvement.
PROFESSIONAL WORK EXPERIENCE
Illumitex, Austin, TX
Illumitex’s LED die designs enable smaller, more usable and efficient lighting solutions through die-level optical integration.
Senior Process Integration Engineer Photolithography Manager/Senior (Sep’2011 – Apr’2012)
• Die development team lead for photolithography R&D and production.
• Worked through tool limitations to meet required product specifications. This included resolving stepper focus issues caused by processing 2” GaN wafers on equipment configured to handle 4” wafers.
• Reduced inline defectivity by over 75% by developing new wafer clean procedures to eliminate residual residue at initial and post photo rework wafer processing.
• Released and qualified new process layers on a Nikon stepper. This accomplishment included evaluation and selection of photo resist and developer chemicals, total process characterization, defining process specifications, and training of factory technicians.
• Collaborated with the design team to quickly evaluate and test new processes, summarize results and implement into the production process flow.
Freescale Semiconductor, Austin, TX
“Freescale Semiconductor is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial and networking markets. The company is based in Austin, Texas, and has design, research and development, manufacturing or sales operations in more than 20 countries.”
Senior Process Engineer- Photolithography: Oakhill (OHT) Fabrication Facility (Feb’2008 –Sep’2011)
• OHT factory FMEA Champion
• Freescale global factory team lead in charge of upgrading and combining tool qualifications and the Equipment tracking system
• Photo Team lead for Statistical Process Control (SPC), FMEA and Scrap Reduction
• Reduced consumption by 30% on several high usage resists by optimizing recipe configurations such as flow times and dispense volumes.
• Reviewed and analyzed inline production and standard tool qualification data to reduce test wafer usage by 35% in addition to reducing tool qualification frequencies by 40%.
• Reduced cross wafer CD variation by 50% by implementing stepper Dose Compensation Mapping to address Etch chamber uniformity issues seen on MEMS production material.
• Identified inline defectivity issues on MEMS over-travel stoppers which could not be detected by end of line testing. Collaborated with the Yield Enhancement and Etch teams to eliminate the issues and set up inline monitoring capability.
• Developed and optimized a new thick resist pre-wet process to address coverage issues on high topography layers. Resist volume was reduced by 50% while eliminating coat inefficiencies.
• Re-characterized the Passivation Layer for LDMOS products to eliminate over-etching of high topography structures resulting in cycle time savings of over 2 days per photo layer.
• Developed and characterized process for IR MEMS products on the SUSS 1X mask aligner and IR metrology tool.
Process Engineer- Etch: Oakhill (OHT) Fabrication Facility (Jan’2006 – Feb’2008)
• Directed Etch SPC Team
• Etch team owner for Gas and Chemical re-qualifications
• Worked with a global Freescale team to qualify second source process gases and release to production for all factories.
• Re-qualified and improved capabilities of previously idled tools by re-characterizing and adjusting process conditions to match other qualified tool chambers.
• Led cross-functional team to create connectivity between Photo reticle throughout rates and Etch end point time limits. Successful implementation resulted in tightened control limits and decreased engineering interdictions by 50%.
• Implemented new SPC monitoring system to detect first wafer effects on plasma asher tools. This code provided auto-disposition of lots, eliminated nuisance failures and reduced the number of overall failures by 15%.
Process Engineer- Photolithography: Oakhill (OHT) Fabrication Facility (Feb’2001 – Jan’2006)
• Qualified ...
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