Summary: Hardware Design Engineer, Hardware Architect, Systems Engineer: C4ISR Systems, Telecom Networks, Enterprise Platforms. Hardware Design Engineer with FPGA (XILINX and Altera), ASIC, PCB, and Enterprise Platform / C4ISR systems design, verification, test, and integration experience. Hardware Design Engineer with experience in Telecom Network, Enterprise, and C4ISR platforms and applications, e.g. Optical/Gb Ethernet, Digital Modems, PHY Chips, Metro Edge Telecom Optical/Ethernet Switches, Routers, Storage Controllers, Multicore Server Processors, Hardware Emulation, Embedded Systems, C4ISR Displays.
Hardware System Architect (2009-2012)
nanobiowave systems (2009-2012). Startup Company Architecture, Statement of Work (SOW) development for nanobiowave systems Automated Cloud Infrastructure. Systems Architect for nanobiowave systems Automated Cloud Infrastructure and the nanobiowave Human Waveform Systems Architecture with Medical Biochemistry Nanobiosensor Technology Libraries.
FPGA Hardware Design Engineer and Hardware Verification Engineer
M.I.T. LINCOLN LABORATORY (Lexington, Massachusetts) (2008)
DVB-S2 Transmitter Waveform Design. FPGA SOC Design of Physical Layer Mapper, Scrambler, Framer for DVB-S2 Digital Video Broadcast Transmitter/Modulator for XILINX VIRTEX-5 SXT95 FPGA with QPSK/8PSK Modulation Functions. ETSI DVB-S2 Specification. Tools/Design Flow: MODELSIM RTL Simulation, SYNPLIFY PRO Logic Synthesis, XILINX VIRTEX-5 SXT95 FPGA, XILINX ISE Foundation. Consultant expertise in SV/OVM/UVM IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.
Systems Engineeer, Hardware Architect, Design, Verification, and Validation Engineer
Independent Technology Platform Innovation Studies (2002-2007).
FPGA, ASIC, SoC, MultiCore IP Hardware Architecture, Design, Verification, and Silicon Validation Engineering Skills Development. FPGA, ASIC, SoC, MultiCore IP Embedded Hardware Architect, IP Functional Block Design, Integration and Test, Embedded Software Design Engineering Skills Development. Developed Technical skills in Synthesizable VERILOG/VHDL and SystemVerilog Testbench Environments, C/C++/Assembly ISR’s for Embedded High Performance Processors, Synthesizable FPGA Testbench Architectures, and Standard ASIC Chip Design Methodologies to facilitate Career Development focusing on Silicon and System Platform Architecture, Design, Verification, and Validation. Developed skills as an FPGA SoC Architect, Design, Verification, and Silicon Validation Engineer using Standard and Application-Specific Embedded Processor Cores, DSP Cores, I/O Cores, Network Processor Architectures, FPGA/ASIC/SOC Synthesizable Design Verification Methodologies, Career Development Strategizing for maximum longterm ROI. Consultant expertise in SV/OVM/UVM IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.
FPGA Hardware Design Engineer
SYCAMORE NETWORKS (Wallingford, CT) (1999-2001)
FPGA Design Engineer, VHDL Coding, MTI Simulation, Synopsys Synthesis, and Lab Debug of Ingress and Egress Paths of DS3 to System Interface. FPGA Design Architecture and Functionality consisted of SONET/Packet Flow Control and External SRAM Lookup Table and SONET/Packet modification. Altera FPGA and Altera Quartus Tool suite. Expertise in SV/OVM/UVM IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure. The Wallingford, CT based Sirrocco Systems, an Optical-Edge Switch Products Start-Up Company, was merged to form the Optical-Edge Switch Product Development Business Unit of Sycamore Networks, a Transport-to-Edge-to-Access Optical Networking Infrastructure Corporation (Chelmsford, MA). Successful Startup Company Buyout (Mergers and Acquisitions).
ASIC Design Verification Simulation Engineer
LUCENT TECHNOLOGIES (North Andover, MA and Allentown, PA) (1999)
ASIC Verification of the SuperMapper ASIC, a SONET STS-1 Mapped to T1/E1, DS2, DS3 and Multiple Standard and Custom System Interfaces for large scale TELCO Switching Platform Access. Tasks included developing ASIC Verification Operations Flow for ASIC RTL Development, Test bench Driver Development in the MTI Simulation Environment, ASIC Verification Operations Development, Test Plan Development, Verification Operations Perl Script Development, and ASIC Verification Team Development. Expertise in SV/OVM/UVM IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.
Multichip FPGA Design Verification Team Leader
EMC (Hopkington, MA) Subsidiary McDATA Corporation, North Ontario, Canada (1998-1999)
Team Lead for Verilog Multichip FPGA Design Verification of Fibre Channel/Switch/Protocol Controller using Verilog VCS. Team Lead for three FPGA verification engineers responsible for detailed Verification Test Plan Development, FPGA Verification Test Bench, and Regression Test Scenario Script Development, VeriSure Code Coverage Analysis (Statement Coverage, Branch Coverage, Path Coverage, Condition Coverage), Verilog module bug diagnosis, location, and code edits with Atria Clearcase verilog source code control. Expertise in SV/OVM/UVM IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.
Verilog ASIC Design Verification Simulation Engineer
FUJITSU Corporation, Acton, MA (1998)
Verilog ASIC Design Verification of Frame Relay over DS3 ASIC Chipset with Channelized/Unchannelized T1/E1/T3E3. ASIC Verification Simulations were executed on the T1/E1/T3/E3 ASIC and the Frame Memory Contoller ASIC which provisioned eight Frame Relay Service Tiers via an ATM Core Switching Hub. Developed T1/E1/T3/E3 Framer Transactor and Design Verification Strategy/ Framework developed for Standalone ASIC-Level Testbenches, ASIC Chipset/System-Level Verification. Expertise in SV/OVM/UVM IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.
Verilog ASIC Design Verification Simulation Engineer
DIGITAL EQUIPMENT CORPORATION, Maynard, MA (1997)
Verilog ASIC Design Verification of DEC/Compaq’s next generation Enterprise Server Chipset. ASIC Verification Simulations were executed on the I/O Spanner ASICs which facilitated the data exchange between the multiprocessor server chipset switch fabric and standard PCI Bus ASICs. Standalone ASIC verification and multiprocessor block (18 ASICs) verification testbeds were developed using verilog VCS, verilog PLI, and Perl Scripts. The Enterprise Server Chipset I/O Spanner block contained the following basic functions: Cached DMA, Cache Coherency State Machines, Multiprocessor Switch Fabric Bus Command Arbitration State Machines, PCI ASIC I/O Command FSMs, TLB Logic, System Interrupts, and I/O CSRs. Expertise in SV/OVM/UVM IC and FPGA Design Verification Methodologies and real-time automated verification hardware emulation platform infrastructure.
Verilog ASIC and Board Hardware Design Verification Simulation Engineer
CABLETRON SYSTEMS, INC., ...
Login or Register to view the full resume.
