Professional Experience:
Organization: Triple Crown Consulting, LLC
Duration: March 2013 – May 2013
Position: IC Layout Engineer
Project:
DC to DC Converter for IRAD (AMS .35um CMOS) for Client TLSI in Huntington, NY
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Implemented layout for Current Sensor, current bias, opamp, comparator and small digital blocks
Assisted in top level wiring including pads
Edited layout of High side and Low Side Drivers to fit design changes
Performed Top Level verification (DRC, DRC-DFM, and LVS) using Assura
Organization: Epoch Microelectronics, Inc.
Duration: October 2007 – June 2012
Position: IC Layout Engineer
•Developed complex IC layout of RF and analog intensive mixed signal ICs
•Corresponded with IC design engineers.
•Managed floor-planning, block layout and evaluation of RF and Mixed Signal Analog circuits.
•Handle the tasks of preparing engineering related documents for future reference
•In-depth knowledge of PCB design through Eagle PCB software
•Assisted senior engineers with task of running simulations (dc, transient, noise) on schematic with back-annotated parasitics or extracted-C or RC views
Projects:
•RF Transceiver SOC for ITS (TSMC 0.13um CMOS)
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Contributed design, simulation and post layout verification of RX, TX, and PLL CML divider/buffer/regulator circuits.
Completed reports and simulation checksheets for assigned blocks
•6-degree of freedom MEMs Sensor ASIC (TSMC 0.18um CMOS)
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Implemented layout of C2V amplifier for Gyro interface.
Contributed layout of bandgap, bandgap/R, constant-Gm, and VT/R voltage/current reference circuits.
Implemented layout using Virtuoso Cadence schematic driven layout tools, and verified the layout using Assura DRC/LVS verification tools.
Assisted with edits for metal-mask change tape-outs.
•TV Tuner IC (TSMC 0.18um CMOS)
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Contributed layout of IF polyphase Filter, Tracking Filter, and Mixer blocks using Virtuoso schematic driven layout tools.
Performed verification using both Assura DRC/LVS and Calibre DRC/LVS tools.
Performed design verification of channel selection baseband filter and made improvements to phase margin of the filter.
Assisted with edits for metal-mask change tape-outs.
•Multi Bit Sigma Delta ADC (TSMC 0.18um CMOS)
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Implemented layout for Sigma Delta ADC
Performed verification using Assura DRC/LVS
Created PCB board for chip test simulations
•Flexible Output Range, Low Power 8 Bit current steering DAC (TSMC 0.18um CMOS)
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Contributed layout for complete DAC
Created PCB board for chip test simulations
Performed verification using Assura DRC/LVS
•10GHz LC VCO (TSMC 0.13um CMOS)
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Contributed to complete layout of VCO
Performed verification using Calibre DRC/LVS
•Four 4GHz VCO for GSM/WCDMA application (TSMC 0.18um CMOS)
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