HARDWARE DEVELOPMENT ENGINEER / ELECTRONICS DESIGN ENGINEER / ELECTRICAL ENGINEER /
HARDWARE DESIGN ENGINEER / PRODUCT DEVELPOMENT ENGINEER / PROJECT ENGINEER / MANUFACTURING TEST / SYSTEM INTEGRATION / SYSTEMS TEST / SYSTEMS VERIFICATION TESTING /
REGRESSION TESTING / COMPONENT ENGINEERING / PRODUCT ENGINEER / PRODUCT MANAGER
I am a Senior Electronics Design Engineer, in R & D Hardware Development. Experience from concept to production release, designing, schematic capture, Bill of Material (BOM), net property assignment, layout component placement, prototyping, testing from board to systems level (SVT), troubleshooting, documenting, and component obsolescence resolution. Work with FPGA Engineers, Software Engineers, Systems Engineers, Component Engineers, Purchasing, Product Line Management (PLM), Customer Technical Assistance Center (CTAC), Documentation Data Management (DDM), and the factory. Create module requirements, specifications, systems level block diagrams, specify new components, Preliminary, Intermediate, and Final Design Review (PDR, IDR, and FDR) presentations, and create rework instructions for ECN/ECOs. I am detail orientated, mechanically inclined, and a team player.
Experience/Skills/Training
• Word • Schematic Capture •Altera Quartus II Training
• Excel • Mentor Graphic DxDesigner • Xilinx Essentials of FPGA Design Training
• PowerPoint •Mentor Graphics Design Architech • Xilinx Designing for Performance Training
• Outlook • Cadence Concept Schematic Capture • Xilinx Embedded Systems Development Training
• Unix • Broadcom BCM Diagnostic Shell Tool • HyperLynx Signal and Power Integrity Training
• GUI • Embedded Systems Board Design 8Bit/32Bit • T-BERD and Tautran Transmission Test Sets
• Breadboards • Prototype Boards • BOM – Bill of Materials
• SRAM • EEPROM • FLASH Memory
• DS1/E1/T1 • Optical and Electrical Interface Board Design • High Speed Digitizing Storage Oscilloscopes
• DS3/E3/T3 • Mixed Signal Digital and Analog Board Design • Spectrum Analyzers
• OC3 SONET • Ethernet PHY • SmartBits 6000B and Acterna IP Test Sets
• SerDes • Ethernet Switch and Layer 2 Testing • 1GbE Gigabit Ethernet Optical and Electrical
• SFP • RS442 • Logic Analyzers
• RS232 • RS485 • Environmental/Temperature Chamber Testing
• I2C • SPI • Systems Level Troubleshooting
• MIIM • PCI • Board Level Component Troubleshooting
• JTAG • Assembly Language Firmware • Multi-Source Component Selection
• EPLD • Drive • Component Obsolescence / Board Re-Design
• FPGA • VHDL • Manufacturing/Factory Product Support
• BGA • Sensors • Documentation
• RoHS • A/D and D/A Converters • Design Review Presentation
• OP-AMPS • Linear Regulators • DC-DC Buck Switching Power Supply
• CODEC • SLIC • Hand Soldering – Excellent Manual Dexterity
• SMT • Thru-Hole • Wire Wrap
• Drill Press • Lathe and Milling Machines • AUTOMOTIVE
Hardware Development Engineer Senior
Alcatel-Lucent, Plano, TX
December, 2006 to April, 2011(Laid off due to reduction in force)
9500MPR - Microwave Packet Radio
• Ethernet Access Switch Board Design Feature Update – PLM Requested New Functions Feasibility Study. Researched standards and technical design requirements for new board features. Responsible for creating requirements document, block diagrams, and presentation slides, to be used in the High Level Design Review presentation. Created initial schematic capture in Mentor Graphics Design Architect and physical parts layout placement in Mentor Graphics Board Station. This database was next used to perform a thermal analysis simulation, of the new board.
• 9500MPT H/L MODEM – Microwave Packet Transport, PLM Requested New Functions Feasibility Study. Researched technical design requirements for new board features. Checked the existing backplane design for interoperability. Meet with component vendors. Worked with mechanical engineers on component height issues. Worked with purchasing, to get cost estimates. Worked with component engineers, specified new connectors, LDO regulators, and I2C components. Investigate preliminary power requirements. Assigned I2C addresses and created memory map. Investigated next generation MODEM IC chip functions, for board layout considerations. Created initial schematic capture in Mentor Graphics Design Architect and physical parts layout placement in Mentor Graphics Board Station. This database was next used to perform a thermal analysis simulation, of the new board, by mechanical engineering. Created requirements document, block diagrams, and presentation slides. As the lead engineer, I held the High Level Design Review presentation meeting.
• 9500MPT H/L MODEM – Microwave Packet Transport, R&D MODEM testing/troubleshooting Xilinx Virtex-4 FPGA, to help group meet schedule target date. Preformed systems level testing, using customer software for provisioning and engineering test GUIs to monitor internal temperature, fan RPM and clock status, on the 9500MSS shelf and 9500MPT H/L MODEM. MODEM testing concentrated on the FPGA’s SERDES eye diagram and clock recovery, synchronization acquisition lockup time. Check channel bandwidths with spectrum analyzer. Tests conducted over temperature, in a temperature chamber, using a high speed digital storage scope with built in eye diagram templates and the SmartBits tester.
• Ethernet Access Switch Board – Designed and Released to Production, supported new product manufacturing production issues. Design included Gigabit Ethernet electrical RJ45 and optical SPF ports, Altera Stratix II GX FPGA, crosspoint switch, Broadcom Switch and PHY devices. 780 and 1152 pin BGAs, on a 14 layer PCB. Researched and specified new devices with component engineering. Created library part shape requests, to CAD librarian. Work with the FPGA engineer on device selection, I/O bank voltage requirement and pin function/location selection, to optimize board layout. Schematic captured the board using Mentor Graphics Design Architect. Assigned net properties and constraints to schematic. Participated in component placement and routing, with the PCB/PWA designer. Worked with Altera FAE on FPGA implementation, board design review. Wrote the board’s test plan document. Checked the new engineering board builds for power supply voltages, ripple noise, reset signals, clock signal integrity, PCI data/address bus signal integrity, SERDES eye diagram compliance, and Layer 2 testing. Hand soldered non BGA components in lab. Modified and updated FPGA test GUI. Tested FPGA control and status registers. Worked closely with software engineering, debugging device drivers and bringing up board. Provide hardware troubleshooting/debugging support to software en...
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