RESUME
PERSONAL
NAME:
SEX: Male
BIRTHDAY: xxx
BIRTHPLACE: xxx
ADDRESS: xxxxx
Mobile: xxx-xxx-xxxx
E-Mail: xxx
Skype: xxx
EDUCATION EXPERIENCE
April,1995 to March,1997 Yokohama National University, Japan,
Graduate School of Engineering, M.S.Degree
April, 1994 to March,1995 Yokohama National University, Japan,
Pre-graduate Student
May,1992 to March, 1994 Tokyo Language School. Japanese Course
Sept. 1981 to July, 1985 Shanghai University, China
Department of Microelectronics. B.S.degree
Sept. 1979 to July, 1981 Shanghai XiangMing High School
EMPLOYMENT HISTORY
Sept. 16, 2012 to now, Free, in New York.
May, 2005 to Sept.15, 2012 Shanghai WeiLing Electronic
Technology Co.,Ltd.
Manager.
March 1, 2004 to June 30. 2004 Sumisho Electronics Co.,Ltd.
Chief Engineer. EDA Engineering Div.
May 10, 2002 to Dec 31. 2003 Data IO Japan
Chief Engineer, EDA Engineering Div.
Oct 1, 2000 to Oct 30, 2001 Alcatel China Ltd.
Senior ASIC Design Engineer
Aug 1, 1999 to Sept 30, 2000 Newave Technology(Shanghai) Co., Ltd
Senior IC Design Engineer
July 1, 1998 to June 29, 1999 AssetCore Technology Co., Ltd
IC Design Engineer
April 1, 1997 to March 29, 1998 Sony LSI Design Inc.
IC Designer
July 1985 to May 1992 Shanghai DongHai Radio Factory
Chief of Quality Section
MAIN TECHINICAL HISTORY
2005.5 ~ 2012.9.15 : Manager, Shanghai WeiLing Electronic Ttechnology Co.,Ltd. Developed EDA including DFM, Hardware Prototyping System, VerilogHDL Simulator, IP business and other application business.
2004.3.1~ 2004.6.30 Sumisho Electronics Co.,Ltd. Chief Engineer. EDA Engineering Div. Responsible for tools of Carbon Design Systems Inc. in Japan area. Act as Co-simulation Technology Support.
2002.5.10~2003.12.31 After employed by Data-IO Japan, Chief Engineer. The work was responsible for ASIC design or design support and managing EDA support. Technically supporting SILOS logic simulator and HyperFault simulator. Answering user’s question which includes digital, transistor level or switch level through mail, telephone or visiting customers. Writing SOC application design using SILOS, Altera’s QuartusII and Xilinx’s ISE. Writing Verilog/SystemC/C Co-Simulation application design. Also translating SILOS and HyperFault’s English document to Japanese. Web-designing for supporting customer. Introducing design solution to customer, pre-sales and post-sales etc.. Also have the experience of repairing ROM writer and ROM writer maintenance.
2000.10.1~2001.10.30 In Alcatel China Ltd. Alcatel Microelectronics, Senior ASIC design engineer. The main works included timing verification for POTs project which used in telecommunication, GSM base-band simulation with VHDL, AMBA protocol based ASP/APB/AHB bus change, modification and simulation. Developing USB 2.0 controller based on system function block design. Bluetooth protocol based wireless IC project verification, PCM interface verification. Tools included Word Processor and Alcatel’s ADS design system.
1999.8.1~2000.9.30 After employed by Newave Technology(Shanghai) CO., Ltd, Senior IC design engineer. I focused on developing Frame IC from algorithm design to test bench design using Verilog based on ITU protocols. Tools included Word processor, Verilog-XL, Design Compiler.
1998.7.1~1999.6.29 After joined AssetCore Technology Co., Ltd, IC design engineer. The main project was ATM implementation with VHDL and RTL function simulation. Tools included Mentor’s Modelsim and Summit’s Visual-VHDL. Using TI’s DSP to build motor controlling board and modify assembler code to drive motor.
1997.4.1~1998.3.29 In Sony LSI Design Inc. IC design engineer. Mainly engaged in digital circuit design, worked on graphical process based memory controller IC which used in digital still camera. The project included verification such as function simulation and timing analysis from Verilog RTL to gate level and chip test. Tools included Verilog-XL, Synopsys’ Design Compiler, PrimeTime and other Sony Design Platform. Also in designing watch, MAX+PLUSII was used to verify the circuit. Schematic design had experienced.
1985.7~1992.5 Shanghai DongHai Radio Factory, Engineer, Chief of Quality Management Section. As a power-semiconductor process engineer include oxidization, etching and so on, worked at manufactory workshop. Then worked as Chief, handling the product QC and process quality.
Login or Register to view the full resume.
