KEY WORDS
Atomic Force Microscopy(AFM), Peak Force Tapping, FPGA/CPLD, VHDL, DSP, Digital Control, Data Acquisition System (DAQs), A/D, D/A converter, LVDS, PECL, High Speed Digital Design
PROFILE
Over 11 years experiences in AFM industry. Key inventor of Bruker revolutionary AFM operation mode, Peak Force Tapping and related technologies which enables material topography, mechanical and electrical mapping at atomic resolution.
Proven track of record of new technology developments with innovations. Excellent problem solving capability to challenging technical issues.
14 years high-speed, low noise board level mixed signal design experience.
Expertise on high-speed digital control system design. Implement algorithm with complex cutting edge FPGA and DSP.
High-Speed Digital Design experience with FPGA/CPLD (from VHDL RTL coding, synthesis to static timing verification), PECL, LVDS and PCIe bus interface.
Experience in high-speed analog and digital mixed signal PCB layout, good understanding in board impedance control, signal integrity, board timing and EMI analysis.
Deep knowledge of analog electronics; Extensive High-Speed, low noise front end sensor and DAQs system design experience.
Work knowledge in Forward Error Coding, communication system simulation with MATLAB & C
Telecommunications background in Gigabit Ethernet, T1/E1, OC3
EXPERIENCE
03/2010 – Present: Staff Engineer, Bruker Nano, Goleta, CA
Leaded Bruker true atomic resolution imaging project. Dramatically reduced the AFM system noise and foresaw the potential of newly invented peak force tapping mode, successfully achieved true atomic resolution with Peak Force Tapping mode. Among those achievements, atomic resolution in ambient enviroment and single atom mechanical mapping were the first in AFM communities.
Participated research and technology developments for new AFM applications. Designed electronics and FPGA firmware for Proof of Concept activities.
03/2002 – 09/2010: Sr. Electrical Engineer, Golden Reward Winner of Veeco Instruments, Goleta, CA
Invented and leaded the implementation of revolutionary AFM operation mode: Peak Force tapping mode and related technologies. Since its introduction to the market, those technologies have been the key driver of growth of corporate revenue.
Architected and leaded the design of Veeco next generation high speed, low noise digital controller NanoScope V. This controller is based on cutting edge FPGA and includes multiple high speed, low noise ADC/DACs as well as front end low noise sensor and signal condition circuitries.
Started from scratch, designed FPGA with VHDL for high speed digital control and signal processing algorithm such as multiple servo feedbacks, DDS, digital Lock-in, Cordic, Log function and Q control for AFM with high end Altera FPGA.
Designed Gigabit Ethernet Line card for high-speed data exchange between digital controller and host PC.
Mentor Interns to design test fixtures
08/2000 – 09/2001: Graduate Research Assistant, University of Toledo, OH
Ultra Wide-band (UWB, DC-1.5GHz) wireless communication simulation
Implemented UWB System FEC Codec (Viterbi Coding & Reed-Solomon Coding)
UWB nonlinear wireless channel modeling.
08/1997 - 08/2000: Hardware Engineer, Guangzhou Telecommunications Corporation, China
Responsible for microprocessor based T1/E1, T3/E3, Fast Ethernet, telephony interface circuit des...
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