Expertise:
•Digital Design, Embedded Systems
•FPGAs (Actel, Xilinx, Altera), SymplifyPro, Modelsim
•RTL - VHDL 90% Verilog 10%
•DSP - FPGA based (DARPA SLAAC - FASTEST)
•PCB - Design (Mentor Expedition(Expert), Cadence, PADS)
•Cockpit Avionics - C17.
•Analog - A/D, D/A, Radar Receiver/Exciter
•EW Systems
•Test Engineering
•MIL-STD-1553, ARINC-429, SPI, I2C, RS-232/485/488,VME,PCI,cPCI,PCIe
•Inertial Navigation – Missile
• Hi-Density 3D packaging – up to 40% reduction in size plus reduction
in weight.
Experience:
Carlton National Resources/Northrup-Grumman
San Diego, California
April 1, 2013 to Sept. 6, 2013
FPGA PCB Design Engineer Contractor
Analysis and VHDLcoding of a ten year old design in a Vertex II 1000, and recreating this design to be functionally equivalent to present design supplied by an outside source. Very challenging
and behind schedule. The design is UVPS and for their radio system on JSF.
BENTLY GLOBAL/Parker Aerospace
Irvine, California
November 11, 2012 to April 1, 2013
FPGA PCB Design Engineer Contractor
Aid to supervise a small group in Design and coding (VHDL) for Motorized surface controllers for new series Gulfstream Airplane.
WIPRO/BAE Systems
Endicott, New York
April 9, 2012 to November 5, 2012
FPGA PCB Design Engineer Contractor
First task to code a Lattice Power Monitor and an Actel (Mircosemi) AX1000 for C-17 RCIP Processor board. The Lattice is coded in ABEL and the RX1000 in VHDL. Most of this work was for Obsolete Component replacement and upgrades. Also creating documents for customer acceptance of total board based on my FPGA design and Power Sequencer Design. Transferred to KC390 to write code and test benches for ACTEL, Altera and XILINX fpga's.
SysPros/L-3 Electrodynamics
1200 Hicks Ave., Rolling Meadows, IL
July 2011 to Sept. 2011
Test and FPGA VHDL Engineer Contractor
First task was to create ATPs for their series of flight data recorders. These recorders had various interfaces from Ethernet to Mil-1553. Later tasked to write a simulation model for a Cypress PSoC chip and 1553 IP be able to verify their FPGA design. Adhered to DO-254 and DO-160 standards.
BELCAN/Hamilton-Sunstrand(UTC)
Harrison Blvd., Rockford, IL
June 2010 to July 2011
System and Design Engineer Contractor
Assigned to many programs. EMI engineering on Cryo Pump for Orion (NASA). Test Set design for characterization of Power Controllers for Orion (NASA). Aid in PDR presentation for EMP and Lighting Supression for Orion. Tools Visio, Excel, Cadence, Hyperlinx and SymplifyPro. FPGA used ACTEL RTAX. Adhered to DO-254 and DO-160 standards.
Systems Pros/Jackson & Tull
Executive Drive, Seabrook, MD
February 2010 to June 2010
Systems Engineer Contractor
Create documentation for the design of Telemetry Imaging System on board ARES launch system for NASA. NASA ARES budget cut ended in project cancellation.
Atlantic Inertial Systems
805 Irving Wick Road
Heath, OH 43056
April 13, 2009 to June 12, 2009
Radiation Design Engineer Contractor
Simplify and design existing Accelerometer (MERA) to be RADIATION HARDENED for final product. Also aid in space packaging of design. Due to economy, contract not awarded and job suspended. AIS sold to Goodrich Aerospace.
Pratt-Whitney-Rocketdyne
555 Discovery Drive/ Redstone Arsenal
6235 Rime Village Drive,
Huntsville, AL 35806
June 2007 to April 10, 2009
System Electronic Design Engineer Contractor
Hired to help in the design of Hardware in Loop (HWIL) System for the development of the New Space Shuttle Engines. First task assigned was to design a test system to test major components for AIRBUS A400 Military Transport. Completed this task then designed a Universal Sensor In-Circuit emulator (80% Analog) boards based on cPCI and Altera EP2C70F896. EDA tools used Altera QUARTUS, Symplify PRO, ModelSim and Mentor Expedition with FPGA Advantage. Knowledgeable in Spacewire and Firewire.
Rockwell-Collins
Cedar Rapids, IA 52405
February 2007 to May 2007.
Senior Electrical Engineer Contractor
Job was to design and code a series of 4 Virtex 5’s and a Vertex 4 for use in a universal SATCOM Modem (Wolverine and HDRF). Funding for this IRAD project was terminated do to loss of awards. EDA Tools used XILINX ISE, Symplify PRO, ModelSim and Mentor Expedition with FPGA Advantage.
Raytheon Missile Systems – Tucson Nov. 2004 to May 3, 2005
Hired by Raytheon May 3, 2005 to Feb 16, 2007
Senior Electrical Engineer II
Lead VHDL FPGA Engineer for EKV STE System Development. Development of Common Electronic Interface (CEI) for all CCA’s in the EKV Electronics Unit (EU). Training of new hires and existing personnel in designing with VHDL for FPGA (present FPGA Vertex II Pro).
Northrop Grumman, Linthicum, MD
April 2003 to Aug 2004
Digital, FPGA and EW Systems Engineer Contractor
Digital Systems Engineering for START and MMA Electronic Warfare systems. Analysis of present ICAP III system SRAs and design recommendations for new digital SRAs for START and MMA using present ICAP III SRAs. Designed and simulated a Receiver/RFExciter FPGA for Common Ku IRAD (Altera STRATIX and Quartus II- VHDL).
Space Micro, Poway, CA
November 2002 to April 2003
Senior Scientist
Proposal writing for SBIR's to Missile Defense Agency, AFRL Albuquerque and NRA to NASA Office of Earth Sciences. Designs for Radiation Hardened Electronics and advanced computing using FPGA's as basic element. This was a non-salaried position.
Science Applications International Corp., Albuquerque, NM
August 1998 - November 2002
Senior Staff Scientist/PI to NASA
Development Engineering assistance to Malleable Signal Processor for the Air Force Research Lab (AFR...
Login or Register to view the full resume.
