Objective
Seeking a position in Electronics. Offering value to a company through my high technical level in engineering, wide knowledge in circuit design techniques and hardworking, proactive behavior.
Education
Bachelor & Master of Science in Telecommunication Engineering. (ABET certified) August 2013
Specialization in Electronics.
Technical University of Madrid, ETSIT-UPM, Spain.
Microelectronics.
(MOS Trts and Model, CMOS logic, Basic Digital Circuits and Characterization, Timing, Latch, Flip-Flop, ROM, PLA, RAM)
Design of Electronic Circuits and Systems.
(Timing, Clock Skew, Jitter and Distribution, Design of Combinational Systems, Adders, Comparators and Multipliers)
Electronics Communication Laboratory.
(Analog Modulations [AM, FM, DSB, SSB], Digital Modulations [ASK, BPSK, QPSK, FSK], Super Heterodyne Transreceiver, Phase Locked Loops and Frequency Sensitizers)
Optical Communications.
(Optical Fibers, FBG, Match-Zehner and Fabry-Perot Interferometer, LD and LED, Photodiodes: p-i-n and APD, SNR and BER, Signal Multiplexing WDM systems)
Advanced Electromagnetic Fields.
(Transverse EM Waves, Homogeneous Waves, Impedance Concept, Incidence of Plane Waves on Obstacles, Guided Waves, Conducted Cylindrical Waveguides, Dielectric Waveguides)
Master of Science in Electrical Engineering. GPA: 3.5/4.0 August 2013
Specialization in Electronics.
Illinois Institute of Technology (IIT), Chicago, IL.
Introduction to VLSI.
(MOS Trt [Length Channel and Non-Ideal], Pseudo MOS, Dynamic CMOS, Power Consumption and Delay, Multi-stage Networks, Logical Effort and Combinational Circuits)
Advanced VLSI Design.
(Dynamic CMOS – 2 Phase, NORA, DCVSL, CPL, MTCMOS, Dual Vt Domino Logic, ZZCMOS, SRAM [6T & PLNA4T], Full Adder [10T & CLRCL], D3L and SPD3L)
Computer Organization & Design.
(Computer Performance, MIPS Instruction Set, Floating Point, ALU Design, Datapath Single-cycle and Control Logic, Multicycle and Control Logic, Microprogramming, Pipeline [Hazards & techniques])
Advanced Computer Architecture.
(MIPS Design and Tradeoffs Instruction Sets, CPU Architecture [Pipeline & Design], Design of Cache & Main Memory [Associative ways, Write Thru & Back, No & Write Allocate, LRU, LFU, FIFO], Design of Storage Systems [Disk], Design of Bus Systems)
High Performance VLSI:IC Systems.
(System-Level Power Reduction [Loop Unrolling & Cache Config,], RTL [Automatic & Enhanced Clock Gating], Power Gating [Single Footer, Stepwise Wake-Up, Two Pass PG Switching Control])
Experience
Software Engineer at Channel IQ September 2013 – Present
Use of software based on Java, Kapow, to build bots.
Extraction of information using knowledge of HTML, CSS sand JavaScript.
Implementation of MySQL and C# as tools to store and manipulate data.
Projects
Design and Synthesis of a DWT data compression block. (IIT) January 2013 – September 2013
Design in VHDL and C of a DWT block using Daubechies coefficients with 4 level depth.
Filtration and compression of the signal with DWT.
Use of the VHDL implementation using Xilinx, to perform the data compression on a FPGA board.
Design and Simulation of a CPU, Cache, Bus and Memory Datapath. (IIT) January 2013 – May 2013
Implementation of a 32-bit instruction PC, IR, CPU, Memory, Cache and FSM in VHDL.
Emphasis on Cache operation, Instruction and Data Cache, Write back and No-Write Allocate Design.
Test of the whole complex with a set of instructions (lw, sw, nor, slt, beq) particularly on Load and Store instructions (Access to Data Cache).
Design and Implementation of SPD3L and D3L Full Adders. (IIT) January 2013 – May 2013
4-bit Full Adder implemented in SPD3L and D3L techniques.
Schematic and layout design using Cadence Virtuoso.
Test and Measur...
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