OBJECTIVE
Seeking a position to be part of a dynamic team that will help in utilizing my knowledge of Computer and Electrical Engineering. I am hard working and motivated and can help contribute effectively to the team. (May 2014) EDUCATION
THE UNIVERSITY OF TEXAS AT DALLAS, Richardson, Texas May 2014
Master of Science in Electrical Engineering GPA 3.5
ACHARYA NAGARJUNA UNIVERSITY, India April 2011 Bachelor of Technology in Electrical and Electronics Engineering GPA 3.6
WORK EXPERIENCE
RF TEST ENGINEER INTERN - GTL USA AUG 2013 – JAN 2014
• Worked for Ericsson in Network Optimization and Performance Field testing of AT& T 4G LTE and WCDMA sites.
• Used ASCOM-TEMS tool to decide the quality of network service by measuring parameters like SINR, RSRP and RSRQ.
• Performed Single site verification and Single site shakedown of 4G LTE networks and analyzed the downlink/uplink throughput and Inter/intra frequency handover.
• Provided recommendation and coordinated with Ericsson team for issue resolution and optimization.
RELEVANT COURSEWORK
Digital VLSI Design ASIC Design Advanced digital logic Analog IC Design Computer Architecture Design Automation of VLSI systems RF & Microwave Circuits Active semi-conductors
Introduction to MEMS RFID & Wireless sensor networks Digital signal processing
TECHNICAL SKILLS
Tools: Cadence tools (Virtuoso, Encounter), Synopsys tools, Hspice, OrCAD, Modelsim, Tetramax, AWR.
Operating Systems: Windows 2000/7, Mac OS X, UNIX, Sun Solaris.
Languages: C/C++, Verilog HDL, Perl scripting.
Technologies: GSM, WCDMA, LTE.
RF Test Tools: Network Analyzer, Oscilloscope, TEMS, RF Scanner.
ACADEMIC PROJECTS
MINI STEREO DIGITAL AUDIO PROCESSOR Aug 2012 – Dec 2012
• Developed architecture for a high-speed and low power MSDAP chip and implemented the designed system using Verilog.
• Verified the system correctness by writing a testbench using Verilog.
• Performed functional simulations using ModelSim and synthesized the designed architecture in Design Vision.
• Implemented using TSMC 0.18um technology.
• Generated a chip layout from Encounter and verified the chip size, power dissipation, clock tree and post-layout timing closure.
IMPLEMENTATION OF CORDIC ALGORITHM USING VLSI DESIGN TECHNIQUES May 2012 – Aug 2012
• Implemented Cordic Algorithm for Calculation of Trigonometric functions using Verilog.
• Designed Standard Cell Library using Cadence by employing IBM 130nm Technology.
• Checked and verified the design using DRC, LVS and Spice netlist is obtained using PEX.
• Gate-level netlist is obtained by design vision using the designed cell library.
• Final Placement and Routing of design is done using Encounter and Timing Analysis is pe...
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