SUMMURY of EXPERIENCE:
8+ years’ experience in complex ASIC/FPGA RTL design/simulation/verification, synthesis, timing analysis of application processor, communication system and high speed data bus product.
3+ years’ experience in SOC prototyping/validation. Knowledgeable of SOC architecture, LPDDR3/DDR3 memory controller, APB peripherals, AXI/AHB bus. Experience in lab test and debugging
10+ years’ experience in all phases of product development from concept to release. Strong communication skills
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WORK EXPERIENCE:
Sr. IC Design Engineer, MARVELL SEMICONDUCTOR 3/2011–present
Responsible for SOC prototyping with components including DDR3/LPDDR3 memory controller/LCD/AUDIO/ISP/VPU/APB peripherals. RTL modification/optimization, synthesis and P&R on the complex multi-FPGAs platform.
Responsible for multi-domain clocking design and timing analysis for SOC prototype
Responsible for simulation tests debugging on prototyping components.
Responsible for bringing up of SOC prototype with Mavell XDB debugger.
Design automation flow for the prototype process using perl/tcsh
Design Engineer, Data Device Corporation. 1/2007 – 3/2011
Designed Advanced Data Handler Block. Asynchronous transfer of messages from multiple real-time communicating components memory to target memory and DMA to host without host intervention to highly improve bus utilization.
Designed Replay. Reconstruct data for an entire bus traffic (pause/loop) from recorded raw/formatted file including parallel to serial, Manchester encoding and timing control.
Design intermessage routines. To allow specific actions and data modifications to happen in real time without having to stop the protocol engine.
Internship, Data Device Corporation 2006 - 2007
Designed MAC-PHY block processing (Tx/Rx) of high-speed data bus network. Including CRC, scramble, Reed-Solomon encoder, c...
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