1801 S 3rd St, Alhambra, CA91803
1-626-863-4458
University of Southern California (USC), CA, U.S. GPA: 4.0
Master of Science in Electrical Engineering
Viterbi School of Engineering
Courses:
Computer Systems Organization (EE457) Ranked 6th of 255
MOS VLSI Circuit Design (EE477) Ranked 8th of 141
Computer Systems Architecture (EE557)
VLSI System Design (EE577a)
Network Processor Design and Programming (EE599)
Digital System Design-Tools and Techniques (EE560) Ranked 5th of 147
VLSI System Design (EE577b)
Diagnosis and Design of Reliable Digital Systems (EE658)
Introduction to Parallel and Distributed Computation (EE452)
Harbin Institute of Technology (HIT), Harbin, P.R.C.
Bachelor in School of Electronics and Information Engineering
Specialty: Electronic Information Engineering
GPA: 89.2/100.0
Related Courses:
Signals and Systems
Digital Signal Processing
Television Principles
Random Signal Analysis
Electronic Circuit for Communication
Digital Logic Circuit and System
Microprocessor Principle
Communication Principles
Digital Image Processing
Information Theory and Coding
Computer Skills: Embeded C, C#, Verilog, SystemVerilog, VHDL, Assembly, Perl, Python, TCL, Pthreads, Xilinx ISE, Modelsim, Chipscope, Quatus II, SignalTap, NiosII, uCOS-II, Keil, NC Verilog, Design Compiler, TetraMax, PrimeTime, Cadence Virtuoso, Conformal, Encounter, MATLAB, Proteus, LATEX, Unix
Experience:
Ktech Telecommunications Inc.
Electronics Engineering Intern (Quatus II, NiosII, uCOS-II, Keil, Verilog, C)
Develop and test a board consisting of Altera Cyclone III FPGA, responsible for channel and program info extract from television transport stream, and NXP microcontroller, responsible for peripheral I/O including buttons, Ethernet, USB
• ATSC Digital Television Broadcast Standard—Program and System Information Protocol
• Test code of microcontroller and FPGA to check the connection to SDRAM, FLASH and DDR2
• Embedded SMTP client to send alert email when trigger condition detected
• Remote firmware upgrading by Ethernet from Windows GUI
Ming Hsieh Department of Electrical Engineering, USC
EE 452 (C, POSIX threads, MPI, CUDA)
• Block matrix multiplication using Pthreads and CUDA parallel computing library
• Parallel algorithm/hardware analysis of prefix sum communication, max finding, merge sort and Cannon’s matrix multiplication
EE 658 (C, ATPG)
• Final project: Automatic Test System consisting of fault list generation and collapsing, gates levelization, test vector generation by D and PODEM ATPG algorithm and parallel and deductive fault simulation
EE 577b (NC-Verilog simulator, Synopsis Design Compiler)
• Final project: DDR2 memory controller and initial engine, support single, block and atomic rd/wr; went through static timing analysis, equivalence verification and auto place and route
• DFT lab: Scan chain insertion by Synopsis DFT Compiler, then ATPG by TetraMax; BIST RTL simulation; Iddq and delay test through Primetime and TetraMax; IEEE1149.1 JTAG controller design and boundary scan cell insertion
• SystemVerilog lab in directed randomization, concurrent assertion and object-oriented programming
• UVM and OVM frame modification to verify a simple sequence detector
• Viterbi decoder algorithm implementation and statement coverage 93.2%
EE 560 (Xilinx ISE, Nexys 3 FPGA board, VHDL):
• OoO (Tomasulo) CPU which dynamically schedules instructions and executes them in out of order fashion but retires them in-order. Design of a Copy-Free check pointing unit to restore the F-RAT in case of a branch misprediction was a major achievement. Also designed issue unit, free-register file, etc. Verification passed through individual unit simulation by Signal Spy in Modelsim, overall behavior simulation and on-board test
• Chip multithreading Project, realizing Round Robin thread select by rotating buffer, thread suspension, rollback and MSHR for non-blocking cache access. Verification passed by both behavior simulation and post synthesis simulation
• MOESI Cache Coherence Protocol for 4 cores connected to a L2-cache through a single bus
• Cache implementation on content addressable memory (CAM) and least recent used unit (LRU)
• Timing constraints on Timing Ignore Group (TIG), set multi-cycle path for multiple subtractions
• MIPS 5-stage pipelined CPU design with BRAMs using shadow and keep register; Two-clock FIFO with BRAM, double synchronization of gray-coded pointer
• Xilinx 8-bit soft-core processor PicoBlaze operation of on-board LEDs by Assembly code
• On-Chip Logic Analyzer, ChipScope, implementation by netlist insertion and HDL instantiation
• File I/O between the PC and the FPGA board using Epp serial I/O protocol
• Interface lab, 4-way handshake, 2-way handshake, FIFO way to understand 2-way handshake and eventually confirm that FIFO way is more robust
EE 599 (Xilinx ISE, Virtex2P FPGA family):
• Measurements of TCP and UDP performance on bandwidth, delay and window size by iperf command and Deterlab network emulated by ns file
• Single core 5-stage p...
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