Rakesh

6/14/2014
Albuquerque, NM

Position Desired

Electronics Engineering
Albuquerque, NM
Yes

Resume

RK Mahto


» Experience Summary
• Strong knowledge of CMOS VLSI Design concepts in device, gate and system levels.
• Adept in EDA tools: Tanner Tools, Cadence, Synopsys, Mentor Graphics.
• Expertise in RTL to GDSII flow at 130nm and180nm IBM processes, TSMC 0.35um HV and 0.35um ON Semi processes.
• Good understanding of ASIC library design and implementation.
• Practical and teaching experience in Digital Design using HDL (VHDL).
• Specialized in device characterization including lab measurement using test equipment’s such as spectrum analyzer and vector network analyzer, test plan development & PCB.
• Successful tape-out experience of mixed-signal IC as well as digital IC.

» Skill Set
EDA Tools: Tanner Tools (L-edit, T-Spice, S-Edit, W-edit, LVS), Cadence Tools Suite (Virtuoso, ADE-Analog Design Environment, Spectre, SpectreRF, Abstract Generator, Encounter Library Characterizer, RTL, Compiler, Encounter, ORCAD, Allegro, Pspice A/D), Mentor graphics tools (ModelSim, Calibre LVS, DRC, PEX), Synopsis Tools (Hspice, Design Analyzer/compiler).
Hardware Description Language: VHDL/Verilog HDL, System C
Packages: Xilinx ISE, Matlab, Labview, NI Multisim, Altera Quartus II
RF Design Tools: Agilent ADS, Microwave Office, Sonnet Lite
Programming/Scripting language: C, C++, C#, Perl, TCL, Java, HTML, DHTML
Lab Equipment: Network Analyzer, Oscilloscope, Spectrum Analyzer, Curve Tracer.

» Education
University of New Mexico, Albuquerque, NM
Ph.D. Computer Engineering, 2014 (Expected)
GPA: 3.45/4.0

California State University, Fullerton, CA
M.S. Computer Engineering, 2009
GPA: 3.77/4.0

» Profession Experience
ASIC design flow in IBM 180nm technology process,
• Designed the standard cells library (no of cells 80) which includes DRC, schematic, LVS, PEX, symbol generation and abstract generation.
• Generated the .lib and analyzed all the cells in the standard cell library by using Encounter Library Characterizer (ELC) for later timing and power analysis.
• Predicted the timing, power analysis, area of the FPU and AES engine by using t...

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