Ted KAO
Address: San Jose, CA 94536
Tel (mobil): 510-493-0410
--------------------------------------------------------------------------------------
OBJECTIVE to obtain Analog/Mixed-Signal Circuit Design Engineer Position.
Summary
15+ years experience in transistor level Analog/Mixed-Signal circuit design engineer. Proficient knowledge of PLL (LC tank and ring oscillator), transceiver PHY, clock data recovery, DLL, and RF transceiver circuits. Quick learner and adaptable to ongoing challenges. Intelligent, honest team player.
EXPERIENCE
•Senior Analog circuit design engineer. 4/2013 – 5/2014
Dolphin Technology.
Developed SerDes IP such as PLL, LDO regulator, bandgap, amplifiers
1. Designed a compact size analog SerDes PLL using 10:1 capacitor multiplier to greatly reduce on-chip loop cap size. 2.4~3.2GHz VCO. Programmable bandwidth setting to fit in different Ref. freq. Guide layout for noise isolation and to meet analog layout requirements. TSMC28nm digital process.
2. Designed analog blocks such as low power supply curvature compensated bandgap, LDO pmos pass device regulator, and opamps for SerDes application. TSMC 28nm and 16nm
digital process.
•Senior Analog/RF circuit design engineer. 2/2006 - 2/2013Sigma Designs.
Developed on CMOS RF front end for UWB and MoCA (Multimedia over Coax Alliance)
2.0(100Mhz data plan)/1.1(50Mhz data plan) OFDM standard in which carrier frequency
range is from 0.4 GHz to 1.6GHz.
1. Designed a LC tank low phase noise VCO/PLL 5GHz and Lo Buffer in UMC 0.18um RF
process. Characterized performance in lab.
2. Designed high linearity class A Pre PA driver with programmable output power.
Up-conversion mixer in high linearity double balanced active type. Down-conversion
mixer in high linearity double balanced active type. VGA for high linearity and fixed gain over PVT variation. Low power supply bandgap reference. TSMC 0.13um and 40nm RF
process. Characterized performance in lab.
3. Designed very low power consumption (uA range) analog circuitry such as Bandgap
reference, comparator, vco (5~20MHz), power on reset for handheld applications.
•Senior Analog/RF circuit design engineer. 2/2004 –2/2006
Blue7 communication, acquired by Sigma Designs at 2006
Developed in CMOS RF front end for UWB (Ultra-Wide Band) OFDM standard in which
carrier frequencies range is 3Ghz~5Ghz.
1. Up-conversion mixer in high linearity double balanced active type. Down-conversion
mixer in high linearity double balanced active type. TSMC 0.13um and 40nm RF process. Characterized performance in lab.
2. Designed high speed programmable 3/4/5bit Flash ADC with sampling freq. 528MHz, and
low power supply bandgap reference. UMC 0.18um RF process. Characterized in lab.
•Senior Analog circuit design engineer. 7/2002 - 2/2004
Alliance Semiconductor
Developed serial link analog front end for SerDes standards such as SATA.
1. Designed SerDes SATA Dual-Loop PLL clock data recovery where PFD loop acquired frequency and then PD loop align phase to sample data. Programmable bandwidth setting and regulator provide VCO power. UMC 0.18um logic process. Characterized performan...
Login or Register to view the full resume.
