Summary
3+ years’ experience in programming with C/C++, Python, MATLAB in Linux environment.
Strong background in Image processing, Machine learning, Computer Architecture, Digital Design and Verification.
Developed machine learning algorithms with next generation computational fabrics (memristors) for pattern recognition.
Familiar with parallel programming with CUDA and implemented superscalar processor architectures.
Technical skills
C, C++, Python, Java CUDA, OpenCL, OpenCV Xyce (Parallel), LTSpice, PSpice
Matlab, Simulink, Octave, Eclipse Cluster Computing Verilog, SystemVerilog, Embedded C
Linux-CentOS, Ubuntu, Windows Multi-threaded programming Altera DE2, 8085, Oscilloscope, Logic Analyzer
Education
University Of Dayton - Dayton, OH
M.S in Electrical and Computer Engineering, May 2015, GPA : 3.37
Thesis: Exploring the Capabilities of Memristor based Crossbars towards Pattern
Recognition Applications.
Relevant coursework:
Advanced Computer Architecture
Digital Circuit Design
Heterogeneous Parallel Computing
SOC Verification with SystemVerilog
Microprocessors & microcontrollers
Machine learning Pattern Recognition
Digital Signal Processing
Digital Image Processing
Algorithms and Data structures.
Gandhi Institute of Technology and Management, Visakhapatnam, AP - India
B.Tech in Electrical and Electronics Engineering, May 2012, GPA: 4.0
Project 1: Location of Faults in Transmission Lines using Fast Fourier Transform
and Discrete Wavelet Transform.
Project 2: Wireless RF-Control of DC Geared Motor.
Independent Study: Coursera, Udemy
Work Experience
Research Assistant Jan, 2013 – Present
High Performance and Neuromorphic Computing Laboratory – University of Dayton
Platform: C/ C++/ Python/ Matlab/ Ohio SuperComputer/ Cluster Computing/ Xyce/ Ltspice [Poster]
Design novel memristor based crossbar for low power computational fabrics.
Examined its application as single layer perceptron, concurrent learning, multilayer classification, deep networks.
Developed a programming based memristor crossbar for evaluation which is similar to its SPICE based model.
Graduate Assistant Jan, 2015 – Present
Digital Lab – University of Dayton
Design web pages for faculty members to present their research details.
Attend regular meetings with faculty members, IT department.
Technical Intern May – June, 2011
Wire Rod Mill – Visakhapatnam Steel Plant, Visakhapatnam, India
Platform: C++/ Matlab/ Simulink/ PLC [Report, Certificate, Letter]
Studied the architecture of the ABB PLC controller which included its I/O systems via the optical S800 module bus and the
communication modules via the communication expansion bus.
Documented a reference guide to provide a deeper understanding of the plant with PLC control (ABB Make AC 800 PEC) and
computer controlled system (Siemens R 30).
Trainee and Intern - Embedded systems design for advanced robotics Summer 2011
Technophilia, Hyderabad, India [Code]
Extensive training in Embedded C, UART, PS/2, RC-5, I2C, SPI, PCB layout and real time concepts of OS vs RTOS.
Explored the AVR series of microcontroller which includes its internal/external interrupts, hardware/software interrupts,
timer and counter, USART, ADC, accessing internal EEPROM and Flash ROM.
Projects/ Research Experience
Computer Architecture, Digital Design:
Superscalar processor architecture based simulator [Code, PPT]
Designed a trace driven execution simulator for an out-of-order superscalar RISC processor incorporating the pipeline stages (Fetch, decode, dispatch, issue, execute, commit), branch prediction, data forwarding, memory system and cache system.
Accelerated the instruction per cycle (IPC) performance by 45 %.
Pipeline an un-pipelined DLX processor architecture
Designed a pipeline structure for an un-pipelined DLX processor architecture using pipeline buffers and data forwarding.
Reduced the total execution time of the DLX processor architecture by 73% as compared to its un-pipelined version.
Optimize superscalar RISC processor using PSATsim [PPT]
Three different processor configurations were analyzed, one to provide high performance, second to have the lowest energy consumption and third to provide the best balance between performance and energy cost.
Obtained optimal architecture parameters suitable for each of the processor configurations under a given area cost budget.
Design and implementation of Digital logic circuits with Altera DE2 FPGA board [Code, PPT]
Designed logic circuits such as 4/16 bit Adder, ALU, Finite state machines (FSM), encoder, decoder, shift register,stack, up/down counter in Verilog using Quartus 2 software and tested on Altera DE2 board.
High performance and Neuromorphic Computing:
Memristor based implementation of single layer perceptron for Image classification
Designed a single layer neural network for image recognition using memristor crossbars.
This system provided 94% accuracy compared to the traditio...
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