OBJECTIVE
Actively seeking full time opportunities in the field of Computer Engineering.
EDUCATION
Stony Brook University (Aug’13 – Dec’14)
• MS in Computer Engineering
• Teaching Assistant: Introduction to Software Engineers (C++, data structures and algorithms) (Jan’14 – May’14)
• Courses: Embedded H/W and S/W Co-Design, Mobile Sensing Applications, Compiler Design, Computer Architecture, Algorithms
TECHNICAL SKILLS
Languages: C/C++, Embedded C, Java, Python, JSP, Servlets, JavaScript, MySQL, Verilog, VHDL
Tools, IDEs and frameworks: Microsoft Visual Studio, PSoC Designer, Air-Crack, Wireshark, Keil, ModelSim, Eclipse, Xilinx, Icarus Verilog, MATLAB, Firebase, Cadence Virtuoso
WORK EXPERIENCE
Project Assistant at Stony Brook University (May’14 – Sep’14)
a. To develop a tool to generate mathematical equations of analog circuits using Python, based on the foundation of Genetic Algorithms.
b. To design and develop games used for research experiments using JavaScript, JQuery, Firebase.
Software Engineer at iGate Global Solutions Ltd. (Feb’13 – Jul ‘13)
Worked on: Java, Servlets, JSP, and Spring Framework 3.0 using MVC architecture.
PROJECTS
Embedded H/W & S/W Co-Design (Aug’14 – Dec’14)
Built an ‘Interaction Recording Badge’ using Embedded C on a PSoC1 development kit. Implemented voice recognition to track conversations with persons of interest, and sound localization to identify the distance of the speaker from the system.
Mobile Sensing Applications (Aug’14 – Dec’14)
Analyzed and processed wireless traffic using Aircrack to estimate campus device population distribution.
Compiler Design (Feb’14 – May’14)
Designed a compiler for E- -, an event processing language. Successfully implemented and integrated various stages of compiler design (lexical, syntax, semantic analysis, code generation, and register allocation), and performed various optimizations in C++.
Computer Architecture (Jan ’14 – May’14)
Designed a dual-issue pipelined multimedia processor (based on the Cell SPU 128-bit architecture) using Verilog. Implemented a vast ISA along with the detection of structural, data and control hazards. Simulated the functionalities of a local store memory, instruction buffer, and various stages of pipelining.
VLSI Physical and Logic Design Automation (Aug’13 – Dec’13)<...
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