SUMMARY
Electrical Engineer working towards a master’s degree with a focus on mixed signal circuit design. Have two years of professional experience in IC mask layout designing. Interested in a career as a Design engineer. Seeking a full time opportunity with an in-depth knowledge of:
RTL to GDS flow and ASIC
Verilog HDL
Analog IC design
CMOS VLSI and Memory Design
Computer Architecture
Physical Design and Verification
EDUCATION
Master of Science, Electrical Engineering, May 2015
Ira A. Fulton Schools of Engineering, Arizona State University. GPA: 3.4
Bachelor of Engineering, Electronics and communication engineering May 2011
KLS Gogte Institute of Technology, Belgaum, India. Percentage: 76.70
WORK EXPERIENCE
PHYSICAL DESIGN AND MASK LAYOUT ENGINEER- INTEL (Through Smartplay Technologies), Bangalore, India 2012-2013
Carbon Canyon: Layout design of the LDO’s in different Flavors in 22nm process using Genesys and Hercules.
Designed floor-plan, placement and layouts for input buffer, analog core block, voltage reference, resistor divider and level shifter using Genesys and Hercules to create the top level LDO’s. Performed the layout verifications of these blocks including LVS, DRC, latch up, IR drop analysis, EM, antenna, density, ERC, DFM and ESD analysis. Designed the layout for ESD protection circuit, power grid routing and shielding.
PHYSICAL DESIGN AND MASK LAYOUT ENGINEER-INTEL (Through Mindtree Ltd), Bangalore, India 2011-2012
Magic Harbor: Layout design of the DACREF, comparators, Operational Transconductance Amplifier (OTA), level shifters, AON in TSMC 130nm process using Cadence and Hercules.
Designed the layouts for all the blocks starting from the area estimation, floorplanning, placement and routing. Verified the blocks for LVS, DRC and density. Collaborated with team members to develop the top level layout. Participated in review sessions held by local team members and onsite members, mentored the new joiners.
ACADEMIC PROJECTS
RTL to GDS flow of a 32 bit MIPS processor through automatic place and route (APR) using Encounter. Spring-14
Synthesized the 32 bit processor using system Verilog and cadence RC compiler. Implemented the layout with DRC, LVS clean and performed static timing analysis (STA) using PrimeTime tool.
Implementation of static Re-reference interval prediction cache replacement- Computer Architecture Fall-14
The cache replacement policy was implemented on GEM5 and tested across few benchmarks. The implementation results were compared and analyzed with the results of “Least Recently Used (LRU)” cache replacement policy.
Design of cross point memory array with RRAM devices and study of NAND, NOR Flash Memory. Fall-14
Ran the write and read operations of the array in HSPICE simulator. Studied the array size effect, Ron effect, IV non-linearity effect on read/write margins. Also studied the scaling trend of the cross point array and compared multi bit vs single bit write.
Design of a 16 entry, 32 bit wide register file (RF) with two read ports and one write port. Spring-14
Designed the register file consisting of two read decoders, one write decoder and the RF array. The RF cell was extracted for the parasitics and simulation and the circuit was optimized for power and performance. Designed the layout for the RF circuit with DRC and LVS clean.
Circuit Design of the Low Dropout Voltage Regulator (LDO) with 1μF load using SPECTRE. Spring-14
Designed t...
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