Dallas, TX/San Francisco, CA
EDUCATION
The University of Texas at Dallas, Richardson, TX December 2014
MS in Electrical Engineering GPA 3.4/4
Relevant Coursework: Physical Design Automation, VLSI Design, Advanced VLSI Design, Computer Architecture, Semiconductor Device, Advanced Digital Logic, Analog IC Design, Introduction to MEMS
University of Utah, Salt Lake City, UT August–December 2011
Transfer student in Electrical Engineering
Northwestern Polytechnical University, Xi’an, China Jun 2012
BS in Microelectronics GPA 3.3/4
ACADEMIC PROJECTS
Programming Project, Circuit Partitioning C, Python
Implemented and optimized Fiduccia-Mattheyses (FM) Algorithm with ibm01-ibm18 net list benchmarks
Shortest execution time and best result among all participants
Over 90% of final cut size reduction in average
10+ optimizations to achieve extremely short execution time under million gate scale net list
1K-bit SRAM VLSI Design
Designed a 1K-bit SRAM with standard 6-T structure in team of two using IBM 130nm process
Minimum memory cell area among the class
Use four stage NAND row decoder, tree style column decoder and voltage deferential sense amplifier
Built personal gate library for the design
23*23-bit Multiplier VLSI Design
Designed a 23*23-bit Multiplier using Booth-2 algorithm in team of two using IBM 130nm process
Achieved signed number multiplication of signed numbers
Use 12:2 compression algorithm to speed up the multiply operations
Cache Performance Optimizatin Computer Architecture
Optimized the CPI for three benchmarks (GCC, Anagram and GO) by configuring six parameters which are L1, L2 cache size, associativity, unified caches, block size and replacement method
Compared the performance of branch predictors and RAS configurations for each benchmark
All benchmarks were tested and configured with Simplescalar 3.0 under Linux environment
FPGA Related
Designed simple calculators using Xilinx’s virtex-5 FPGA and Verilog
SKILLS
Languages & Algorithms
Proficient in C and Verilog RTL.
Have experience in algorithms including graph algorithms, dynamic programming etc.
Hands on Python, VHDL
Package
Skilled at using Cadenc...
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